About Headquartered in Ottawa, supports the electronic design community across Canada and internationally, specializing in ASIC and FPGA design, verification, and embedded software development. We strengthen our clients' engineering teams and accelerate the delivery of complete, production ready designs.

We are adaptable, efficient, and built around exceptional technical talent. Our continued growth reflects the trust our clients place in us, and we are currently searching globally for a Senior Physical Design Engineer with deep expertise in place and route.
About the EngagementYou will join as an employee and work on behalf of one of our clients, an industry leader building advanced silicon platforms for next generation AI infrastructure. The work pairs leading edge CMOS design with the bandwidth and power demands of modern AI, and the client partners with the world's foremost foundries to bring frontier designs to production. Further details are shared with candidates under confidentiality during the interview process.

This engagement places you at the center of that work, delivering world-class ASICs on the most demanding technology nodes in the industry.
About the PositionAs a Senior Physical Design Engineer, you will own backend implementation from netlist to GDSII on challenging blocks and sub-systems. You will apply advanced flows and techniques on single-digit FinFET technology nodes, working alongside a strong and experienced team to bring complex designs to closure. This is a senior, fully remote role, and you may be located anywhere.
Key Responsibilities

• Run place and route implementation flows and analyze the results.
• Create effective floorplans that support physically aware synthesis.
• Drive designs to timing closure and run physical verification.
• Debug issues spanning tools, timing constraints, DFT, and design.
• Partner with the design team to improve RTL and make it implementation friendly.
• Implement and apply timing ECOs.
• Run PrimeTime and analyze timing reports.
• Develop strategies to optimize power and area.
• Run IR-drop analysis and identify optimal strategies to improve it.
• Interface with analog and front-end teams to align on shared objectives.

Key Qualifications

• 8 or more years of relevant experience in ASIC digital place and route.
• Recent, hands-on experience with leading EDA tools and advanced flows (Synopsys and Cadence).
• Strong understanding of advanced FinFET technology nodes, DRC rules, and node-specific P&R requirements.
• Practical experience with floorplanning.
• Solid grasp of CTS concepts and the ability to design clocks to meet timing requirements.
• Working knowledge of IR-drop optimization strategies.
• Experience with timing closure and ECO implementation (PT-ECO or Tweaker experience is an asset).
• Strong scripting skills.
• Exposure to several of the following: synthesis, StarRC, PT DMSA, RedHawk, Calibre, and formal verification (LEC or Formality).
• A track record as a self-starter who also works well within a team.

Remote WorkThis role is fully remote and open to candidates in any location. You will collaborate with distributed engineering teams across time zones, so strong written communication, self-direction, and the discipline to deliver independently are essential.
Why Work With UsWe offer challenging, stimulating technical work with companies that lead the world in technology and innovation. At , we know our strength lies in the people who join us, so we foster an environment where everyone is trusted, valued, and engaged. We also believe work-life balance matters, and we give our engineers demanding, rewarding roles while leaving room for family, friends, and life beyond work.